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| HM-6518/883 March 1997 1024 x 1 CMOS RAM Description The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6518/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features * This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Low Power Standby . . . . . . . . . . . . . . . . . . . . 50W Max * Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min * TTL Compatible Input/Output * High Output Drive - 2 TTL Loads * High Noise Immunity * On-Chip Address Register * Two-Chip Selects for Easy Array Expansion * Three-State Output Ordering Information PACKAGE CERDIP TEMP. RANGE -55oC to +125oC PART NUMBER HM1-6518/883 PKG. NO. F18.3 Pinout HM-6518/883 (CERDIP) TOP VIEW S1 E A0 A1 A2 A3 A4 Q GND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5 PIN A E W S D Q DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data Input Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 2986.1 6-85 HM-6518/883 Functional Diagram A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 G 32 GATED COLUMN DECODER AND DATA I/O D LATCH A L W A E 5 A 5 Q Q GATED ROW DECODER 32 32 x 32 MATRIX D A LATCHED ADDRESS REGISTER S1, S2 A0 A1 A2 A3 A4 NOTES: 1. All lines positive logic - active high. 2. Three-state buffers: A high output active. 3. Data latches: L high Q = D; Q Latches on rising edge of L. 4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E. 6-86 HM-6518/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. HM-6518/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER Output Low Voltage SYMBOL VOL (NOTE 1) CONDITIONS VCC = 4.5V, IOL = 3.2mA VCC = 4.5V, IOH = -0.4mA VCC = 5.5V, VI = GND or VCC VCC = 5.5V, VO = GND or VCC VCC = 2.0V, E = VCC, IO = 0mA, VI = VCC or GND VCC = 5.5V, (Note 2), E = 1MHz, IO = 0mA, VI = VCC or GND VCC = 5.5V, IO = 0mA, VI = VCC or GND GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 1, 2, 3 -55oC TA +125oC 5 10 4 A A mA MIN MAX 0.4 UNITS V Output High Voltage VOH 1, 2, 3 2.4 - V A A Input Leakage Current II 1, 2, 3 -1.0 +1.0 Output Leakage Current IOZ 1, 2, 3 -1.0 +1.0 Data Retention Supply Current HM-6518B/883 HM-6518/883 Operating Supply Current ICCDR 1, 2, 3 ICCOP Standby Supply Current ICCSB 1, 2, 3 -55oC TA +125oC - 10 A NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 6-87 HM-6518/883 TABLE 2. HM-6518/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) CONDITIONS VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V, Note 3 VCC = 4.5 and 5.5V PARAMETER Chip Enable Access Time Address Access Time Chip Select Output Enable Time Write Enable Output Disable Time Chip Select Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time SYMBOL (1) TELQV GROUP A SUBGROUPS 9, 10, 11 HM-6518B/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN - HM-6518/883 MIN - MAX 180 MAX 250 UNITS ns (2) TAVQV 9, 10, 11 - 180 - 250 ns (3) TSLQX 9, 10, 11 5 - 5 - ns (4) TWLQZ VCC = 4.5 and 5.5V 9, 10, 11 -55oC TA +125oC - 120 - 160 ns (5) TSHQZ VCC = 4.5 and 5.5V 9, 10, 11 -55oC TA +125oC - 120 - 160 ns (6) TELEH VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V VCC = 4.5 and 5.5V 9, 10, 11 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 180 - 250 - ns (7) TEHEL 9, 10, 11 100 - 100 - ns (8) TAVEL 9, 10, 11 0 - 0 - ns (9) TELAX 9, 10, 11 40 - 50 - ns Data Setup Time (10) TDVWH 9, 10, 11 80 - 110 - ns Data Hold Time (11) TWHDX VCC = 4.5 and 5.5V (12) TWLSH VCC = 4.5 and 5.5V (13) TWLEH VCC = 4.5 and 5.5V (14) TSLWH VCC = 4.5 and 5.5V (15) TELWH VCC = 4.5 and 5.5V (16) TWLWH VCC = 4.5 and 5.5V (17) TELEL VCC = 4.5 and 5.5V 9, 10, 11 0 - 0 - ns Chip Select Write Pulse Setup Time Chip Enable Write Pulse Setup Time Chip Select Write Pulse Hold Time Chip Enable Write Pulse Hold Time Write Enable Pulse Width Read or Write Cycle Time 9, 10, 11 100 - 130 - ns 9, 10, 11 100 - 130 - ns 9, 10, 11 100 - 130 - ns 9, 10, 11 100 - 130 - ns 9, 10, 11 100 - 130 - ns 9, 10, 11 280 - 350 - ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; input rise and fall times: 5ns (max); input and output timing reference level: 1.5V; output load: -1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 6-88 HM-6518/883 TABLE 3. HM-6518/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER Input Capacitance SYMBOL CI CONDITIONS VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground NOTE 1 TEMPERATURE TA = +25oC TA = +25oC MIN MAX 6 UNITS pF Output Capacitance CO 1 - 10 pF NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 Timing Waveforms (8) TAVEL A (9) TELAX VALID TELEL (17) TEHEL (7) E HIGH TELEH (6) TEHEL (7) (8) TAVEL NEXT W D TELQV (1) TAVQV (2) Q S1, S2 PREVIOUS DATA TSHQZ 1 HIGH Z VALID OUTPUT LATCHED (5) TSLOX (3) (5) TSHQZ HIGH Z TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE 6-89 HM-6518/883 TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 H L L E H S1 H X L L L H W X H H H H X A X V X X X X D X X X X X X OUTPUTS Q Z Z X V V Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Output Latched Device Disabled, Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) 5 X H V X Z NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. In the HM-6518/883 read cycle the address information is latched into the on chip registers on the falling edge of E (T = 0). Minimum address setup and hold time requirements must be met. After the required hold time the addresses may change state without affecting device operation. In order for the output to be read S1, S2 and E must be low, W must be high. When E goes high the output data is latched into an on chip register. Taking either or both S1 or S2 high, forces the output buffer to a high impedance state. The output data may be re-enabled at any time by taking S1 and S2 low. On the falling edge of E the data will be unlatched. Timing Waveforms (8) TAVEL A TEHEL (7) (9) TELAX VALID TELEL (17) TELEH (6) TEHEL (7) (8) TAVEL NEXT E TWLEH (13) TELWH (15) TWLWH (16) W TDVWH (10) D HIGH Z TSLWH (14) S1, S2 TIME REFERENCE TWLSH (12) VALID DATA TWHDX (11) Q -1 0 1 FIGURE 2. WRITE CYCLE 2 3 4 5 6-90 HM-6518/883 TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L X X X E H S1 X X L W X X L L X X X A X V X X X X V D X X V V X X X OUTPUTS Q Z Z Z Z Z Z Z FUNCTION Memory Disabled Cycle Begins, Addresses are Latched Write Mode has Begun Data is Written Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high. The write cycle is initiated by the falling edge of E which latches the address information into the on chip registers. The write portion of the cycle is defined as E, W, S1 and S2 being low simultaneously. W may go low anytime during the cycle provided that the write enable pulse setup time (TWLEH) is met. The write portion of the cycle is terminated by the first rising edge of either E, W, S1 or S2. Data setup and hold times must be referenced to the terminating signal. If a series of consecutive write cycles are to be performed, the W line may remain low until all desired locations have been written. When this method is used, data setup and hold times must be referenced to the rising edge of E. By positioning the W pulse at different times within the E low time (TELEH), various types of write cycles may be performed. If the E low time (TELEH) is greater than the W pulse (TWLWH), plus an output enable time (TSLQX), a combination read write cycle is executed. Data may be modified an indefinite number of times during any write cycle (TELEH). The data input and data output pins may be tied together for use with a common I/O data bus structure. When using the RAM in this method allow a minimum of one output disable time (TWLQZ) after W goes low before applying input data to the bus. This will ensure that the output buffers are not active. Test Load Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. 6-91 HM-6518/883 Burn-In Circuit HM-6518/883 CERDIP VCC F0 F0 F3 F4 F5 F6 F7 F2 1 2 3 4 5 6 7 8 9 S1 E A0 A1 A2 A3 A4 Q GND VCC 18 S2 17 D 16 W 15 A9 14 A8 13 A7 12 A6 11 A5 10 F0 F2 F1 F12 F11 F10 F9 F8 C1 NOTES: All resistors 47k 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2. . . . F12 = F11 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C1 = 0.01F Min. 6-92 HM-6518/883 Die Characteristics DIE DIMENSIONS: 130 x 150 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.342 x 105 A/cm2 Metallization Mask Layout HM-6518/883 E A0 S1 VCC S2 D W A1 A9 A2 A3 A8 A7 A4 Q GND A5 A6 NOTE: Pin numbers correspond to DIP package only. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-93 |
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